1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device, and particularly to a structure of a portion of a synchronous semiconductor memory device for controlling input/output operation of internal data.
2. Description of the Background Art
FIG. 10 schematically shows an entire structure of a conventional synchronous semiconductor memory device. Referring to FIG. 10, the synchronous semiconductor memory device includes a memory array 1 having a plurality of dynamic type memory cells arranged in rows and columns. Although the structure of the memory cells included in this memory array 1 is not shown, generally 1 transistor/1 capacitor type memory cells are employed.
The synchronous semiconductor memory device further includes an input buffer circuit 2 which incorporates externally applied control signals, that is, a row address strobe signal ZRAS, a column address strobe signal ZCAS, and write enable signal ZWE in synchronization with externally and repeatedly applied clock signals CLK to generate an internal control signal, a command decoder 4 which determines the states of the internal control signals applied from the input buffer circuit 2 to generate a signal for activating a designated internal operation, a readout control circuit 6 activated in response to readout operation instruction signal R from command decoder 4 to generate a readout operation activation signal READ for activating an operation of reading out data of a selected memory cell of memory array 1, and a write control circuit 8 activated in response to a write instruction signal W applied from command decoder 4 to generate a write operation activation signal WRITE for activating an operation of writing data to a selected memory cell of memory array 1.
Input buffer circuit 2 incorporates externally applied control signals ZRAS, ZCAS and ZWE in synchronization with the rise of clock signal CLK and generates internal control signals each in the form of a one-shot pulse signal according to the state of these external control signals. Command decoder 4 decodes this internal control signals applied from input buffer circuit 2 in the form of one-shot pulse to determine the designated internal operation. In other words, in the synchronous semiconductor memory device, the operation to be executed within this device is designated by the combination of the states of the external control signals at the time of rise of clock signal CLK. Here, clock signal CLK may either be an externally applied clock signal or an internal clock signal obtained by buffering this externally applied clock signal.
The synchronous semiconductor memory device further includes an address buffer 18 which incorporates an externally applied address signal AD in synchronization with clock signal CLK to generate an internal address signal, a cell selecting circuit 20 activated in response to a cell selecting operation activation signal from command decoder 4 to select a corresponding memory cell in memory array 1 in accordance with the internal address signal applied from address buffer 18, a write circuit 10 activated in response to write operation activation signal WRITE from write control circuit 8 to write an internal write data applied from input buffer circuit 14 successively to a selected memory cell of memory array 1, and a readout circuit 12 activated in response to readout operation activation signal READ from readout control circuit 6 to successively read out data of a selected memory cell of memory array 1 and to apply the data to output buffer circuit 16.
Normally, write circuit 10 and readout circuit 12 respectively have a plurality of registers and conduct the data stored in these registers in synchronization with the clock signal. There are various data transfer sequences for these write circuit 10 and readout circuit 12, but in this specification, description is simply made that when activated write circuit 10 and readout circuit 12 perform data writing or data reading with a predetermined sequence in synchronization with clock signal CLK.
Input buffer circuit 14 operates in synchronization with clock signal CLK and incorporates external write data DQ (D) applied to data input/output terminal 21 for application to write circuit 10. Output buffer circuit 16 is activated in response to data output enable signal OEM applied from output control circuit 22, buffers the internal readout data applied from readout circuit 12 in synchronization with the clock signal and conducts this buffered data to data input/output terminal 21.
Output control circuit 22 delays readout operation activation signal READ applied from readout control circuit 6 for a prescribed time period (CAS latency) to produce data output enable signal OEM. CAS latency indicates the number of cycles of clock signal CLK required after application of a read command (that is, set of states by which data readout operation is designated by external control signals ZRAS, ZCAS and ZWE) until appearance of valid data DQ(Q) at data input/output terminal 21. More specifically, valid data appears at input/output terminal 21 upon expiration of CAS latency after the application of the read command.
In this synchronous semiconductor memory device, externally applied control signals ZRAS, ZCAS and ZWE are incorporated in synchronization with external clock signal CLK applied periodically and repeatedly to designate this internal operation. Address signal AD is also incorporated in synchronization with clock signal CLK. Internal operation timing is determined by the clock signal, and data input and data output are also performed in synchronization with clock signal CLK. Accordingly, there is no need to take into consideration the timing margin for skew of external control signals ZRAS, ZCAS and ZWE as well as address signal AD (since the defined timings of these signals are determined at the time of the rise of clock signal CLK), so that the internal operation can be started in a faster timing. In addition, since data are also input and output in synchronization with clock signal CLK, data can be input and output in a faster speed.
FIG. 11 is a diagram showing an example of a structure of readout control circuit 6 in FIG. 10. Referring to FIG. 11, readout control circuit 6 includes a burst length counter 6a activated in response to internal readout operation instruction signal R applied from command decoder 4 shown in FIG. 10 to count clock signals CLK to a predetermined number (i.e., burst length), and a flip-flop 6b set in response to activation of internal readout instruction signal R and reset in response to reset signal RST (R) which is a count-up signal from burst length counter 6a. Readout operation activation signal READ is output from this flip-flop 6b. The burst length counted at burst length counter 6a indicates the number of data which can be read out successively upon data reading when a read command is applied thereto once.
Flip-flop 6b includes an inverter 6ba receiving readout operation instruction signal R, an inverter 6bb receiving write operation instruction signal W, an NAND circuit 6bc receiving an output signal of inverter 6ba at its one input, and an NAND circuit 6bd receiving an output signal of NAND circuit 6bc, an output signal of inverter 6bb and reset signal RST(R) applied from burst length counter 6a through an inverter 6be. An output signal of NAND circuit 6bd is applied to the other input of NAND circuit 6bc.
The write operation instruction signal W is generated (that is, activated) from command decoder 4 upon the rise of clock signal CLK when external control signals ZRAS, ZCAS and ZWE are set at predetermined states and data write operation is designated. Readout operation activation signal READ is output from NAND circuit 6bc. This readout control circuit 6 is set when readout operation instruction signal R is activated and is reset when reset signal RST (R) from burst length counter 6a is activated. Accordingly, the activation period of readout operation activation signal READ is determined by the burst length counted by burst length counter 6a.
FIG. 12 shows an example of a structure of write control circuit 8 in FIG. 10. Referring to FIG. 12, write control circuit 8 includes a burst length counter 8a activated upon activation of write instruction signal W to count a burst length, and a flip-flop 8b set upon activation of write instruction signal W and reset upon activation of reset signal RST (W) from burst length counter 8a. Internal write operation activation signal WRITE is output from this flip-flop 8b.
Flip-flop 8b includes an inverter 8ba receiving write instruction signal W, an inverter 8bb receiving readout instruction signal R, an NAND circuit 8bc receiving an output signal of inverter 8ba at its one input to output write operation activation signal WRITE, and an NAND circuit 8bd receiving an output signal of NAND circuit 8bc, an output signal of inverter 8bb, and reset signal RST (W) from burst length counter 8a applied via an inverter 8be. An output signal of this NAND circuit 8bd is applied to the other input of NAND circuit 8bc.
Burst length counter 8a counts the burst length at the time when data write operation is performed. The operations of readout control circuit 6 and write control circuit 8 shown in FIGS. 11 and 12 will now be described hereinbelow, with reference to FIG. 13 which is a timing chart for these operations. Here, it is assumed that the burst length is 4 for both reading and writing operations.
In the period of clock cycle #0, active command (memory cell selecting operation start instruction signal) is already provided. Cell selecting circuit 20 is activated in the synchronous semiconductor memory device and a memory cell would be at a selected state in memory cell array 1.
In clock cycle #1, a write command is applied so as to activate write operation instruction signal W from command decoder 4 for a prescribed period. In response to this activation of write operation instruction signal W, flip-flop 8 is set and write operation activation signal WRITE is activated at H level. At this time, burst length counter 8a is also activated to start the counting operation of clock signal CLK. According to this write command, a column selecting circuit included in cell selecting circuit 20 selects a column of the memory cell. Input buffer circuit 14 incorporates an external write data DQ (D0) applied to data input/output terminal 21 and provides this data to write circuit 10. Write circuit 10 is activated in response to write operation activation signal WRITE to write the write data from this input buffer circuit 14 to a selected memory cell of memory array 1. During the period in which this write operation activation signal WRITE is in activation, write circuit 10 successively writes the write data applied from input buffer circuit 14 in synchronization with clock signal CLK to selected memory cell of memory array 1.
In clock cycle #5, reset signal RST (W) from burst length counter 8a is activated, and write operation activation signal WRITE is reset at L level. In this clock cycle #5, external write data is not applied, and thus write operation of this write circuit 10 is inhibited even when input buffer circuit 14 operates according to clock signal CLK, so as to prevent writing of undefined data. More particularly, in the data write cycle, write circuit 10 internally writes the data from input buffer circuit 14 to a selected memory cell of memory array 1 with a delay of 1 clock cycle per each data writing.
In clock cycle #7, when read command is applied, internal readout instruction signal R from command decoder 4 is activated to attain H level for a prescribed period, and in response to this activation, flip-flop 6b is set to activate readout operation activation signal READ to attain H level. In response to this activation of readout operation activation signal READ, a selecting operation for a memory cell in memory array 1 is performed, and the data of this selected memory cell is readout by readout circuit 12.
Output control circuit 22 delays this readout operation activation signal READ for a prescribed period (CAS latency, i.e., one clock cycle) and activates data output enable signal OEM to attain H level. Output buffer circuit 16 is activated in response to this activation of data output enable signal OEM and conducts the data which is successively readout from readout circuit 12 to data input/output terminal 21. Accordingly, data Q0, Q1, Q2 and Q3 are successively readout from clock cycle #9.
After burst length counter 6a has counted clock signal CLK four times, reset signal RST (R) is activated to attain H level in clock cycle #11. Thus, readout circuit 12 is inactivated. At this time, data output enable signal OEM is still in an activated state at H level, and in clock cycle #12, data Q3 is output to data input/output terminal 21 via output buffer circuit 16. After this readout of data Q3, data output enable signal OEM is inactivated in clock cycle #12.
At the time of this data readout, the period between the application of a read command and the first output of a valid data, that is, the period between clock cycle #7 to clock cycle #9, is called the CAS latency.
By the operation described above, it is made possible to input or output four data (burst length 4) successively in synchronization with clock signal CLK.
As shown in FIGS. 11 and 12, burst length counters are provided in readout control circuit 6 and write control circuit 8, respectively. Reset of flip-flop 6b is performed by internal write instruction signal W as well as by reset signal RST (R) for the following reason. If, write command is applied after the read command is applied and data write operation is started before burst length counter 6a completes counting the burst length, readout circuit 12 has to be inactivated so as to stop the data readout operation. In addition, reset of flip-flop 8b is performed by readout instruction signal R as well as by reset signal RST (W) in write control circuit 8 as shown in FIG. 12 for the following reason. After the write command is applied, if a read command is newly applied before burst length counter 8a finishes counting the burst length, this write circuit 10 has to be inactivated so as to stop the data write operation. The operation as described above in which a command designating a different access mode is provided before input or output of the burst length data is referred to as an "interruption."
In addition to such situations, there may be a difference between the burst length at the time of readout operation and the burst length at the time of write operation. To accommodate such difference, respective control circuitries for data readout operation and for data write operation are separately provided.
However, as shown in FIGS. 11 and 12, readout control circuit 6 and write control circuit 8 are provided with burst length counters 6a and 8a. These burst length counters 6a and 8a are generally formed of clock shift circuits which shift readout operation instruction signal R or write operation instruction signal W in synchronization with clock signal CLK, occupying a relatively large area. Accordingly, when burst length counters 6a and 8a are respectively provided to readout control circuit 6 and write control circuit 8, the area occupied by the portion for controlling the data input/output operation would be made large, which is a significant disadvantage for the implementation of a highly integrated synchronous semiconductor memory device which occupies only a small area.